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stm32 /stm32h5 /STM32H503 /RCC /RCC_APB3RSTR

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Interpret as RCC_APB3RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SBSRST 0 (B_0x0)LPUART1RST 0 (B_0x0)I3C2RST 0 (B_0x0)LPTIM1RST 0 (B_0x0)VREFRST

VREFRST=B_0x0, LPTIM1RST=B_0x0, LPUART1RST=B_0x0, I3C2RST=B_0x0, SBSRST=B_0x0

Description

RCC APB3 peripheral reset register

Fields

SBSRST

SBS block reset Set and reset by software.

0 (B_0x0): does not reset the SBS block (default after reset)

1 (B_0x1): resets the SBS block
LPUART1RST

LPUART1 block reset Set and reset by software.

0 (B_0x0): does not reset the LPUART1 block (default after reset)

1 (B_0x1): resets the LPUART1 block
I3C2RST

I3C2RST block reset Set and reset by software.

0 (B_0x0): does not reset the I3C2RST block (default after reset)

1 (B_0x1): resets the I3C2RST block
LPTIM1RST

LPTIM1 block reset Set and reset by software.

0 (B_0x0): does not reset the LPTIM1 block (default after reset)

1 (B_0x1): resets the LPTIM1 block
VREFRST

VREF block reset Set and reset by software.

0 (B_0x0): does not reset the VREF block (default after reset)

1 (B_0x1): resets the VREF block

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32