stm32 /stm32h5 /STM32H503 /RCC /RCC_BDCR

LSE oscillator enabled Set and reset by software.

0 (B_0x0): LSE oscillator OFF (default after Backup domain reset)

1 (B_0x1): LSE oscillator ON

LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0.

0 (B_0x0): LSE oscillator not ready (default after Backup domain reset)

1 (B_0x1): LSE oscillator ready

LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)

0 (B_0x0): LSE oscillator not bypassed (default after Backup domain reset)

1 (B_0x1): LSE oscillator bypassed

LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0).

0 (B_0x0): lowest drive (default after Backup domain reset)

1 (B_0x1): medium-low drive

2 (B_0x2): medium-high drive

3 (B_0x3): highest drive

LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON.

0 (B_0x0): CSS on 32 kHz oscillator OFF (default after Backup domain reset)

1 (B_0x1): CSS on 32 kHz oscillator ON

LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator.

0 (B_0x0): no failure detected on 32 kHz oscillator (default after Backup domain reset)

1 (B_0x1): failure detected on 32 kHz oscillator

low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.

0 (B_0x0): LSE in analog mode (default after Backup domain reset)

1 (B_0x1): LSE in digital mode (do not use if RTC is active).

RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).

0 (B_0x0): no clock (default after Backup domain reset)

1 (B_0x1): LSE selected as RTC clock

2 (B_0x2): LSI selected as RTC clock

3 (B_0x3): HSE divided by RTCPRE value selected as RTC clock

RTC clock enable Set and reset by software.

0 (B_0x0): rtc_ck disabled (default after Backup domain reset)

1 (B_0x1): rtc_ck enabled

VSwitch domain software reset Set and reset by software.

0 (B_0x0): reset not activated (default after Backup domain reset)

1 (B_0x1): resets the entire VSW domain

Low-speed clock output (LSCO) enable Set and cleared by software.

0 (B_0x0): LSCO output disabled

1 (B_0x1): LSCO output enabled

Low-speed clock output selection Set and cleared by software.

0 (B_0x0): LSI clock selected

1 (B_0x1): LSE clock selected

LSI oscillator enable Set and cleared by software.

0 (B_0x0): LSI oscillator off

1 (B_0x1): LSI oscillator on

LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.

0 (B_0x0): LSI oscillator not ready

1 (B_0x1): LSI oscillator ready