stm32 /stm32h5 /STM32H503 /RCC /RCC_CCIPR5

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Interpret as RCC_CCIPR5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ADCDACSEL 0 (B_0x0)DAC1SEL 0 (B_0x0)RNGSEL 0 (B_0x0)FDCAN1SEL 0 (B_0x0)CKPERSEL

RNGSEL=B_0x0, CKPERSEL=B_0x0, FDCAN1SEL=B_0x0, DAC1SEL=B_0x0, ADCDACSEL=B_0x0

Description

RCC kernel clock configuration register

Fields

ADCDACSEL

ADC and DAC kernel clock source selection others: reserved, the kernel clock is disabled

0 (B_0x0): rcc_hclk selected as kernel clock (default after reset)

1 (B_0x1): sys_ck selected as kernel clock

2 (B_0x2): pll2_r_ck selected as kernel clock

3 (B_0x3): hse_ck selected as kernel clock

4 (B_0x4): hsi_ker_ck selected as kernel clock

5 (B_0x5): csi_ker_ck selected as kernel clock

DAC1SEL

DAC1 sample and hold clock source selection

0 (B_0x0): dac_hold_ck selected as kernel clock (default after reset)

1 (B_0x1): dac_hold_ck selected as kernel clock

RNGSEL

RNG kernel clock source selection

0 (B_0x0): hsi48_ker_ck selected as kernel clock (default after reset)

1 (B_0x1): pll1_q_ck selected as kernel clock

2 (B_0x2): lse_ck selected as kernel clock

3 (B_0x3): lsi_ker_ck selected as kernel clock

FDCAN1SEL

FDCAN1 kernel clock source selection

0 (B_0x0): hse_ck selected as kernel clock (default after reset)

1 (B_0x1): pll1_q_ck selected as kernel clock

2 (B_0x2): pll2_q_ck selected as kernel clock

3 (B_0x3): reserved, the kernel clock is disabled

CKPERSEL

per_ck clock source selection

0 (B_0x0): hsi_ker_ck selected as kernel clock (default after reset)

1 (B_0x1): csi_ker_ck selected as kernel clock

2 (B_0x2): hse_ck selected as kernel clock

3 (B_0x3): reserved, the per_ck clock is disabled

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