stm32 /stm32h5 /STM32H503 /RCC /RCC_PLL2DIVR

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Interpret as RCC_PLL2DIVR

PLL2R=B_0x0, PLL2Q=B_0x0, PLL2P=B_0x0

Description

RCC PLL1 dividers register

Fields

PLL2N	Multiplication factor for PLL2VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). … … Others: reserved 3 (B_0x3): PLL2N = 4 4 (B_0x4): PLL2N = 5 5 (B_0x5): PLL2N = 6 128 (B_0x80): PLL2N = 129 (default after reset) 511 (B_0x1FF): PLL2N = 512
PLL2P	PLL2 DIVP division factor Set and reset by software to control the frequency of the pll2_p_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): pll2_p_ck = vco2_ck 1 (B_0x1): pll2_p_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_p_ck = vco2_ck / 3 3 (B_0x3): pll2_p_ck = vco2_ck / 4 127 (B_0x7F): pll2_p_ck = vco2_ck / 128
PLL2Q	PLL2 DIVQ division factor Set and reset by software to control the frequency of the pll2_q_ck clock. These bits can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): pll2_q_ck = vco2_ck 1 (B_0x1): pll2_q_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_q_ck = vco2_ck / 3 3 (B_0x3): pll2_q_ck = vco2_ck / 4 127 (B_0x7F): pll2_q_ck = vco2_ck / 128
PLL2R	PLL2 DIVR division factor Set and reset by software to control the frequency of the pll2_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL2ON = 0 and PLL2RDY = 0). … 0 (B_0x0): pll2_r_ck = vco2_ck 1 (B_0x1): pll2_r_ck = vco2_ck / 2 (default after reset) 2 (B_0x2): pll2_r_ck = vco2_ck / 3 3 (B_0x3): pll2_r_ck = vco2_ck / 4 127 (B_0x7F): pll2_r_ck = vco2_ck / 128

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