CKPOL=B_0x0, PCMSYNC=B_0x0, I2SSTD=B_0x0, I2SCFG=B_0x0, I2SMOD=B_0x0, MCKOE=B_0x0, DATFMT=B_0x0, CHLEN=B_0x0, WSINV=B_0x0, FIXCH=B_0x0, DATLEN=B_0x0, ODD=B_0x0
SPI/I2S configuration register
| I2SMOD | I2S mode selection 0 (B_0x0): SPI mode is selected 1 (B_0x1): I2S/PCM mode is selected |
| I2SCFG | I2S configuration mode others, not used 0 (B_0x0): slave - transmit 1 (B_0x1): slave - receive 2 (B_0x2): master - transmit 3 (B_0x3): master - receive 4 (B_0x4): slave - Full Duplex 5 (B_0x5): master - Full Duplex |
| I2SSTD | I2S standard selection For more details on I2S standards, refer to 0 (B_0x0): I2S Philips standard. 1 (B_0x1): MSB justified standard (left justified) 2 (B_0x2): LSB justified standard (right justified) 3 (B_0x3): PCM standard |
| PCMSYNC | PCM frame synchronization 0 (B_0x0): short frame synchronization 1 (B_0x1): long frame synchronization |
| DATLEN | data length to be transferred 0 (B_0x0): 16-bit data length 1 (B_0x1): 24-bit data length 2 (B_0x2): 32-bit data length 3 (B_0x3): Not allowed |
| CHLEN | channel length (number of bits per audio channel) 0 (B_0x0): 16-bit wide 1 (B_0x1): 32-bit wide |
| CKPOL | serial audio clock polarity 0 (B_0x0): the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK. 1 (B_0x1): the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK. |
| FIXCH | fixed channel length in slave 0 (B_0x0): the channel length in Slave mode is different from 16 or 32 bits (CHLEN not taken into account) 1 (B_0x1): the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN) |
| WSINV | word select inversion This bit is used to invert the default polarity of WS signal. WS is LOW. In PCM mode the start of frame is indicated by a rising edge. WS is HIGH. In PCM mode the start of frame is indicated by a falling edge. 0 (B_0x0): in I2S Philips standard, Left channel is transfered when WS is LOW, and right channel when WS is HIGH. In MSB or LSB justified mode, Left channel is transfered when WS is HIGH, and right channel when 1 (B_0x1): in I2S Philips standard, Left channel is transfered when WS is HIGH, and right channel when WS is LOW.In MSB or LSB justified mode, Left channel is transfered when WS is LOW, and right channel when |
| DATFMT | data format 0 (B_0x0): The data inside the SPI_RXDR or SPI_TXDR are right aligned 1 (B_0x1): The data inside the SPI_RXDR or SPI_TXDR are left aligned. |
| I2SDIV | I2S linear prescaler I2SDIV can take any values except the value 1, when ODD is also equal to 1. Refer to for details |
| ODD | odd factor for the prescaler Refer to for details 0 (B_0x0): Real divider value is = I2SDIV *2 1 (B_0x1): Real divider value is = (I2SDIV * 2) + 1 |
| MCKOE | master clock output enable 0 (B_0x0): Master clock output is disabled 1 (B_0x1): Master clock output is enabled |