stm32 /stm32h5 /STM32H503 /TIM1 /TIM1_CCMR2_Output

Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).

0 (B_0x0): CC3 channel is configured as output

1 (B_0x1): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3

2 (B_0x2): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4

3 (B_0x3): CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Output compare 3 fast enable

Output compare 3 preload enable

OC3M[2:0]: Output compare 3 mode These bits define the behavior of the output reference signal tim_oc3ref from which tim_oc3 and tim_oc3n are derived. tim_oc3ref is active high whereas tim_oc3 and tim_oc3n active level depends on CC3P and CC3NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=‘00’ (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from ‘frozen’ mode to ‘PWM’ mode. On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC3M active bits take the new value from the preloaded bits only when a COM event is generated.

0 (B_0x0): Frozen - The comparison between the output compare register TIMx_CCR3 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

1 (B_0x1): Set channel 3 to active level on match. tim_oc3ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3).

2 (B_0x2): Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3).

3 (B_0x3): Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3.

4 (B_0x4): Force inactive level - tim_oc3ref is forced low.

5 (B_0x5): Force active level - tim_oc3ref is forced high.

6 (B_0x6): PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNTTIMx_CCR3 else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=‘0’) as long as TIMx_CNTTIMx_CCR3 else active (tim_oc3ref=‘1’).

7 (B_0x7): PWM mode 2 - In upcounting, channel 3 is inactive as long as TIMx_CNTTIMx_CCR3 else active. In downcounting, channel 3 is active as long as TIMx_CNTTIMx_CCR3 else inactive.

Output compare 3 clear enable

Capture/compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).

0 (B_0x0): CC4 channel is configured as output

1 (B_0x1): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4

2 (B_0x2): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3

3 (B_0x3): CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)

Output compare 4 fast enable

Output compare 4 preload enable

OC4M[2:0]: Output compare 4 mode Refer to OC3M[3:0] bit description

Output compare 4 clear enable

OC3M[3]

OC4M[3]