stm32 /stm32h5 /STM32H503 /TIM1 /TIM1_SMCR

SMS[2:0]: Slave mode selection

0 (B_0x0): Slave mode disabled - if CEN = 1’ then the prescaler is clocked directly by the internal clock.

1 (B_0x1): Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.

2 (B_0x2): Quadrature encoder mode 2, x2 mode - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level.

3 (B_0x3): Quadrature encoder mode 3, x4 mode - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input.

4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.

5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high.

6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset).

7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter.

OCREF clear selection This bit is used to select the OCREF clear source.

0 (B_0x0): tim_ocref_clr_int is connected to the tim_ocref_clr input

1 (B_0x1): tim_ocref_clr_int is connected to tim_etrf

TS[2:0]: Trigger selection This bitfield is combined with TS[4:3] bits. This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See Table 605: TIMx internal trigger connection for more details on tim_itrx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.

0 (B_0x0): Internal Trigger 0 (tim_itr0)

1 (B_0x1): Internal Trigger 1 (tim_itr1)

2 (B_0x2): Internal Trigger 2 (tim_itr2)

3 (B_0x3): Internal Trigger 3 (tim_itr3)

4 (B_0x4): tim_ti1 Edge Detector (tim_ti1f_ed)

5 (B_0x5): Filtered Timer Input 1 (tim_ti1fp1)

6 (B_0x6): Filtered Timer Input 2 (tim_ti2fp2)

7 (B_0x7): External Trigger input (tim_etrf)

Master/slave mode

0 (B_0x0): No action

1 (B_0x1): The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event.

External trigger filter This bit-field then defines the frequency used to sample tim_etrp signal and the length of the digital filter applied to tim_etrp. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:

0 (B_0x0): No filter, sampling is done at f DTS

1 (B_0x1): f SAMPLING =f tim_ker_ck , N=2

2 (B_0x2): f SAMPLING =f tim_ker_ck , N=4

3 (B_0x3): f SAMPLING =f tim_ker_ck , N=8

4 (B_0x4): f SAMPLING =f DTS /2, N=6

5 (B_0x5): f SAMPLING =f DTS /2, N=8

6 (B_0x6): f SAMPLING =f DTS /4, N=6

7 (B_0x7): f SAMPLING =f DTS /4, N=8

8 (B_0x8): f SAMPLING =f DTS /8, N=6

9 (B_0x9): f SAMPLING =f DTS /8, N=8

10 (B_0xA): f SAMPLING =f DTS /16, N=5

11 (B_0xB): f SAMPLING =f DTS /16, N=6

12 (B_0xC): f SAMPLING =f DTS /16, N=8

13 (B_0xD): f SAMPLING =f DTS /32, N=5

14 (B_0xE): f SAMPLING =f DTS /32, N=6

15 (B_0xF): f SAMPLING =f DTS /32, N=8

External trigger prescaler External trigger signal tim_etrp frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce tim_etrp frequency. It is useful when inputting fast external clocks on tim_etr_in.

0 (B_0x0): Prescaler OFF

1 (B_0x1): tim_etr_in frequency divided by 2

2 (B_0x2): tim_etr_in frequency divided by 4

3 (B_0x3): tim_etr_in frequency divided by 8

External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with tim_trgi connected to tim_etrf (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, tim_trgi must not be connected to tim_etrf in this case (TS bits must not be 00111). Note: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is tim_etrf.

0 (B_0x0): External clock mode 2 disabled

1 (B_0x1): External clock mode 2 enabled. The counter is clocked by any active edge on the tim_etrf signal.

External trigger polarity This bit selects whether tim_etr_in or tim_etr_in is used for trigger operations

0 (B_0x0): tim_etr_in is non-inverted, active at high level or rising edge.

1 (B_0x1): tim_etr_in is inverted, active at low level or falling edge.

SMS[3]

0 (B_0x0): Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock.

1 (B_0x1): Quadrature encoder mode 1, x2 mode- Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.

TS[4:3]

0 (B_0x0): Internal Trigger 0 (tim_itr0)

1 (B_0x1): Internal Trigger 1 (tim_itr1)

2 (B_0x2): Internal Trigger 2 (tim_itr2)

3 (B_0x3): Internal Trigger 3 (tim_itr3)

SMS preload enable This bit selects whether the SMS[3:0] bitfield is preloaded

0 (B_0x0): SMS[3:0] bitfield is not preloaded

1 (B_0x1): SMS[3:0] preload is enabled

SMS preload source This bit selects whether the events that triggers the SMS[3:0] bitfield transfer from preload to active

0 (B_0x0): The transfer is triggered by the Timer’s Update event

1 (B_0x1): The transfer is triggered by the Index event