CC4S=B_0x0, CC3S=B_0x0
TIM2 capture/compare mode register 2 [alternate]
| CC3S | Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 0 (B_0x0): CC3 channel is configured as output 1 (B_0x1): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3 2 (B_0x2): CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4 3 (B_0x3): CC3 channel is configured as input, tim_ic3 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| OC3FE | Output compare 3 fast enable |
| OC3PE | Output compare 3 preload enable |
| OC3M1 | Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) |
| OC3CE | Output compare 3 clear enable |
| CC4S | Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). 0 (B_0x0): CC4 channel is configured as output 1 (B_0x1): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4 2 (B_0x2): CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3 3 (B_0x3): CC4 channel is configured as input, tim_ic4 is mapped on tim_trc. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) |
| OC4FE | Output compare 4 fast enable |
| OC4PE | Output compare 4 preload enable |
| OC4M1 | Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) |
| OC4CE | Output compare 4 clear enable |
| OC3M2 | Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) |
| OC4M2 | Output compare 4 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) |