TSEN=B_0x0, VBATEN=B_0x0, CKMODE=B_0x0, DUAL=B_0x0, VREFEN=B_0x0, PRESC=B_0x0, MDMA=B_0x0, DMACFG=B_0x0
ADC common control register
| DUAL | Dual ADC mode selection 0 (B_0x0): Independent mode 1 (B_0x1): Combined regular simultaneous + injected simultaneous mode 2 (B_0x2): Combined regular simultaneous + alternate trigger mode 3 (B_0x3): Combined interleaved mode + injected simultaneous mode 5 (B_0x5): Injected simultaneous mode only 6 (B_0x6): Regular simultaneous mode only 7 (B_0x7): Interleaved mode only 9 (B_0x9): Alternate trigger mode only |
| DELAY | Delay between 2 sampling phases |
| DMACFG | DMA configuration (for dual ADC mode) 0 (B_0x0): DMA One Shot mode selected 1 (B_0x1): DMA Circular mode selected |
| MDMA | Direct memory access mode for dual ADC mode 0 (B_0x0): MDMA mode disabled 2 (B_0x2): MDMA mode enabled for 12 and 10-bit resolution 3 (B_0x3): MDMA mode enabled for 8 and 6-bit resolution |
| CKMODE | ADC clock mode 0 (B_0x0): adc_ker_ck (x = 1/2) (Asynchronous clock mode), generated at product level (refer to Section6: Reset and clock control (RCC)) 1 (B_0x1): adc_hclk/1 (Synchronous clock mode). 2 (B_0x2): adc_hclk/2 (Synchronous clock mode) 3 (B_0x3): adc_hclk/4 (Synchronous clock mode) |
| PRESC | ADC prescaler 0 (B_0x0): input ADC clock not divided 1 (B_0x1): input ADC clock divided by 2 2 (B_0x2): input ADC clock divided by 4 3 (B_0x3): input ADC clock divided by 6 4 (B_0x4): input ADC clock divided by 8 5 (B_0x5): input ADC clock divided by 10 6 (B_0x6): input ADC clock divided by 12 7 (B_0x7): input ADC clock divided by 16 8 (B_0x8): input ADC clock divided by 32 9 (B_0x9): input ADC clock divided by 64 10 (B_0xA): input ADC clock divided by 128 11 (B_0xB): input ADC clock divided by 256 |
| VREFEN | Vless thansub>REFINTless than/sub> enable 0 (B_0x0): Vless thansub>REFINTless than/sub> channel disabled 1 (B_0x1): Vless thansub>REFINTless than/sub> channel enabled |
| TSEN | Vless thansub>SENSEless than/sub> enable 0 (B_0x0): Temperature sensor channel disabled 1 (B_0x1): Temperature sensor channel enabled |
| VBATEN | VBAT enable 0 (B_0x0): Vless thansub>BATless than/sub> channel disabled 1 (B_0x1): Vless thansub>BATless than/sub> channel enabled |