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stm32 /stm32h5 /STM32H523 /CRS /CRS_CFGR

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Interpret as CRS_CFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RELOAD0FELIM0 (B_0x0)SYNCDIV 0 (B_0x0)SYNCSRC 0 (B_0x0)SYNCPOL

SYNCSRC=B_0x0, SYNCPOL=B_0x0, SYNCDIV=B_0x0

Description

CRS configuration register

Fields

RELOAD

Counter reload value
FELIM

Frequency error limit
SYNCDIV

SYNC divider

0 (B_0x0): SYNC not divided (default)

1 (B_0x1): SYNC divided by 2

2 (B_0x2): SYNC divided by 4

3 (B_0x3): SYNC divided by 8

4 (B_0x4): SYNC divided by 16

5 (B_0x5): SYNC divided by 32

6 (B_0x6): SYNC divided by 64

7 (B_0x7): SYNC divided by 128
SYNCSRC

SYNC signal source selection

0 (B_0x0): crs_sync_in_1 selected as SYNC signal source

1 (B_0x1): crs_sync_in_2 selected as SYNC signal source

2 (B_0x2): crs_sync_in_3 selected as SYNC signal source

3 (B_0x3): crs_sync_in_4 selected as SYNC signal source
SYNCPOL

SYNC polarity selection

0 (B_0x0): SYNC active on rising edge (default)

1 (B_0x1): SYNC active on falling edge

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32