WHITMRST=B_0x0, RHITMEN=B_0x0, EN=B_0x0, CACHEINV=B_0x0, WHITMEN=B_0x0, STARTCMD=B_0x0, RHITMRST=B_0x0, CACHECMD=B_0x0, RMISSMEN=B_0x0, WMISSMEN=B_0x0, HBURST=B_0x0, RMISSMRST=B_0x0, WMISSMRST=B_0x0
DCACHE control register
| EN | enable 0 (B_0x0): cache disabled 1 (B_0x1): cache enabled |
| CACHEINV | full cache invalidation 0 (B_0x0): no effect 1 (B_0x1): invalidate entire cache (all cache lines valid bit = 0) |
| CACHECMD | cache command maintenance operation (cleans and/or invalidates an address range) 0 (B_0x0): no operation 1 (B_0x1): clean range 2 (B_0x2): invalidate range 3 (B_0x3): clean and invalidate range |
| STARTCMD | starts maintenance command (maintenance operation defined in CACHECMD). 0 (B_0x0): command operation (cache maintenance) finished 1 (B_0x1): start maintenance command (cache maintenance) |
| RHITMEN | read-hit monitor enable 0 (B_0x0): cache read-hit monitor switched off. 1 (B_0x1): cache read-hit monitor enabled |
| RMISSMEN | read-miss monitor enable 0 (B_0x0): cache read-miss monitor switched off. 1 (B_0x1): cache read-miss monitor enabled |
| RHITMRST | read-hit monitor reset 0 (B_0x0): no effect 1 (B_0x1): reset cache read-hit monitor |
| RMISSMRST | read-miss monitor reset 0 (B_0x0): no effect 1 (B_0x1): reset cache read-miss monitor |
| WHITMEN | write-hit monitor enable 0 (B_0x0): cache write-hit monitor switched off. 1 (B_0x1): cache write-hit monitor enabled |
| WMISSMEN | write-miss monitor enable 0 (B_0x0): cache write-miss monitor switched off. 1 (B_0x1): cache write-miss monitor enabled |
| WHITMRST | write-hit monitor reset 0 (B_0x0): no effect 1 (B_0x1): reset cache write-hit monitor |
| WMISSMRST | write-miss monitor reset 0 (B_0x0): no effect 1 (B_0x1): reset cache write-miss monitor |
| HBURST | output burst type for cache master port read accesses 0 (B_0x0): WRAP 1 (B_0x1): INCR |