Regviz

stm32 /stm32h5 /STM32H523 /DCACHE /DCACHE_SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DCACHE_SR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H533/DCACHE/DCACHE_SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BUSYF 0 (B_0x0)BSYENDF 0 (B_0x0)ERRF 0 (B_0x0)BUSYCMDF 0 (B_0x0)CMDENDF

ERRF=B_0x0, BSYENDF=B_0x0, BUSYCMDF=B_0x0, CMDENDF=B_0x0, BUSYF=B_0x0

Description

DCACHE status register

Fields

BUSYF

full invalidate busy flag

0 (B_0x0): cache not busy on a CACHEINV operation

1 (B_0x1): cache executing a full invalidate CACHEINV operation
BSYENDF

full invalidate busy end flag

0 (B_0x0): cache busy or in idle

1 (B_0x1): full invalidate CACHEINV operation finished
ERRF

cache error flag

0 (B_0x0): no error

1 (B_0x1): an error occurred during the operation (eviction or clean operation write-back error).
BUSYCMDF

command busy flag

0 (B_0x0): cache not busy on a CACHECMD command

1 (B_0x1): cache busy on a CACHECMD command (clean and/or invalidate an address range)
CMDENDF

command end flag

0 (B_0x0): cache busy or in idle

1 (B_0x1): CACHECMD command finished

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32