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stm32 /stm32h5 /STM32H523 /DCACHE /DCACHE_WHMONR

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Interpret as DCACHE_WHMONR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WHITMON

Description

DCACHE write-hit monitor register

Fields

WHITMON

cache write-hit monitor counter

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32