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stm32 /stm32h5 /STM32H523 /DCMI /DCMI_RIS

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Interpret as DCMI_RIS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FRAME_RIS 0 (B_0x0)OVR_RIS 0 (B_0x0)ERR_RIS 0 (VSYNC_RIS)VSYNC_RIS 0 (LINE_RIS)LINE_RIS

OVR_RIS=B_0x0, ERR_RIS=B_0x0, FRAME_RIS=B_0x0

Description

DCMI raw interrupt status register

Fields

FRAME_RIS

Capture complete raw interrupt status

0 (B_0x0): No new capture

1 (B_0x1): A frame has been captured.
OVR_RIS

Overrun raw interrupt status

0 (B_0x0): No data buffer overrun occurred

1 (B_0x1): A data buffer overrun occurred and the data FIFO is corrupted.
ERR_RIS

Synchronization error raw interrupt status

0 (B_0x0): No synchronization error detected

1 (B_0x1): Embedded synchronization characters are not received in the correct order.
VSYNC_RIS

DCMI_VSYNC raw interrupt status
LINE_RIS

Line raw interrupt status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32