stm32 /stm32h5 /STM32H523 /FDCAN /FDCAN_CCCR

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Interpret as FDCAN_CCCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)INIT 0 (B_0x0)CCE 0 (B_0x0)ASM 0 (B_0x0)CSA 0 (B_0x0)CSR 0 (B_0x0)MON 0 (B_0x0)DAR 0 (B_0x0)TEST 0 (B_0x0)FDOE 0 (B_0x0)BRSE 0 (B_0x0)PXHD 0 (B_0x0)EFBI 0 (B_0x0)TXP 0 (B_0x0)NISO

BRSE=B_0x0, MON=B_0x0, DAR=B_0x0, ASM=B_0x0, PXHD=B_0x0, FDOE=B_0x0, NISO=B_0x0, CCE=B_0x0, EFBI=B_0x0, TEST=B_0x0, INIT=B_0x0, TXP=B_0x0, CSR=B_0x0, CSA=B_0x0

Description

FDCAN CC control register

Fields

INIT

Initialization

0 (B_0x0): Normal operation

1 (B_0x1): Initialization started

CCE

Configuration change enable

0 (B_0x0): The CPU has no write access to the protected configuration registers.

1 (B_0x1): The CPU has write access to the protected configuration registers (while CCCR.

ASM

ASM restricted operation mode

0 (B_0x0): Normal CAN operation

1 (B_0x1): Restricted operation mode active

CSA

Clock stop acknowledge

0 (B_0x0): No clock stop acknowledged

1 (B_0x1): FDCAN can be set in power down by stopping APB clock and kernel clock.

CSR

Clock stop request

0 (B_0x0): No clock stop requested

1 (B_0x1): Clock stop requested.

MON

Bus monitoring mode

0 (B_0x0): Bus monitoring mode disabled

1 (B_0x1): Bus monitoring mode enabled

DAR

Disable automatic retransmission

0 (B_0x0): Automatic retransmission of messages not transmitted successfully enabled

1 (B_0x1): Automatic retransmission disabled

TEST

Test mode enable

0 (B_0x0): Normal operation, register TEST holds reset values

1 (B_0x1): Test Mode, write access to register TEST enabled

FDOE

FD operation enable

0 (B_0x0): FD operation disabled

1 (B_0x1): FD operation enabled

BRSE

FDCAN bit rate switching

0 (B_0x0): Bit rate switching for transmissions disabled

1 (B_0x1): Bit rate switching for transmissions enabled

PXHD

Protocol exception handling disable

0 (B_0x0): Protocol exception handling enabled

1 (B_0x1): Protocol exception handling disabled

EFBI

Edge filtering during bus integration

0 (B_0x0): Edge filtering disabled

1 (B_0x1): Two consecutive dominant tq required to detect an edge for hard synchronization

TXP

If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame.

0 (B_0x0): disabled

1 (B_0x1): enabled

NISO

Non ISO operation

0 (B_0x0): CAN FD frame format according to ISO11898-1

1 (B_0x1): CAN FD frame format according to Bosch CAN FD Specification V1.

Links

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