PDIV=B_0x0
FDCAN CFG clock divider register
| PDIV | input clock divider 0 (B_0x0): Divide by 1 1 (B_0x1): Divide by 2 2 (B_0x2): Divide by 4 3 (B_0x3): Divide by 6 4 (B_0x4): Divide by 8 5 (B_0x5): Divide by 10 6 (B_0x6): Divide by 12 7 (B_0x7): Divide by 14 8 (B_0x8): Divide by 16 9 (B_0x9): Divide by 18 10 (B_0xA): Divide by 20 11 (B_0xB): Divide by 22 12 (B_0xC): Divide by 24 13 (B_0xD): Divide by 26 14 (B_0xE): Divide by 28 15 (B_0xF): Divide by 30 |