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stm32 /stm32h5 /STM32H523 /FLASH /FLASH_EDATA1R_PRG

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Interpret as FLASH_EDATA1R_PRG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EDATA1_STRT 0 (B_0x0)EDATA1_EN

EDATA1_EN=B_0x0, EDATA1_STRT=B_0x0

Description

FLASH data sector configuration Bank1

Fields

EDATA1_STRT

EDATA1_STRT contains the start sectors of the flash high-cycle data area in Bank1 There is no hardware effect to those bits.

0 (B_0x0): The last sector of Bank1 is reserved for flash high-cycle data

1 (B_0x1): The two last sectors of Bank1 are reserved for flash high-cycle data

2 (B_0x2): The three last sectors of Bank1 are reserved for flash high-cycle data
EDATA1_EN

Bank1 flash high-cycle data enable

0 (B_0x0): No flash high-cycle data area

1 (B_0x1): Flash high-cycle data is used

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32