CLKDIV=B_0x0, ADDSET=B_0x0, BUSTURN=B_0x0, DATLAT=B_0x0, DATAHLD=B_0x0, ACCMOD=B_0x0
SRAM/NOR-flash chip-select timing register for bank 1
| ADDSET | Address setup phase duration 0 (B_0x0): ADDSET phase duration = 0 HCLK clock cycle 15 (B_0xF): ADDSET phase duration = 15 HCLK clock cycles (default value after reset) |
| ADDHLD | Address-hold phase duration 1 (B_0x1): ADDHLD phase duration =1 HCLK clock cycle 2 (B_0x2): ADDHLD phase duration = 2 HCLK clock cycle 15 (B_0xF): ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) |
| DATAST | Data-phase duration 1 (B_0x1): DATAST phase duration = 1 HCLK clock cycles 2 (B_0x2): DATAST phase duration = 2 HCLK clock cycles 255 (B_0xFF): DATAST phase duration = 255 HCLK clock cycles (default value after reset) |
| BUSTURN | Bus turnaround phase duration 0 (B_0x0): BUSTURN phase duration = 1 HCLK clock cycle added 15 (B_0xF): BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) |
| CLKDIV | Clock divide ratio (for FMC_CLK signal) 0 (B_0x0): FMC_CLK period= 1x HCLK period 1 (B_0x1): FMC_CLK period = 2 HCLK periods 2 (B_0x2): FMC_CLK period = 3 HCLK periods 15 (B_0xF): FMC_CLK period = 16 HCLK periods (default value after reset) |
| DATLAT | (see note below bit descriptions): Data latency for synchronous memory 0 (B_0x0): Data latency of 2 CLK clock cycles for first burst access 15 (B_0xF): Data latency of 17 CLK clock cycles for first burst access (default value after reset) |
| ACCMOD | Access mode 0 (B_0x0): Access mode A 1 (B_0x1): Access mode B 2 (B_0x2): Access mode C 3 (B_0x3): Access mode D |
| DATAHLD | Data hold phase duration 0 (B_0x0): DATAHLD phase duration = 1 HCLK clock cycle (default) 1 (B_0x1): DATAHLD phase duration = 2 HCLK clock cycle 2 (B_0x2): DATAHLD phase duration = 3 HCLK clock cycle 3 (B_0x3): DATAHLD phase duration = 4 HCLK clock cycle |