TAR3=B_0x0, TCLR=B_0x0, PBKEN=B_0x0, ECCPS=B_0x0, PWID=B_0x0, TAR=B_0x0, PWAITEN=B_0x0, ECCEN=B_0x0
NAND flash control registers
| PWAITEN | Wait feature enable bit 0 (B_0x0): disabled 1 (B_0x1): enabled |
| PBKEN | NAND flash memory bank enable bit 0 (B_0x0): Corresponding memory bank is disabled (default after reset) 1 (B_0x1): Corresponding memory bank is enabled |
| PTYP | Memory type 1 (B_0x1): NAND flash (default after reset) |
| PWID | Data bus width 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits (default after reset). |
| ECCEN | ECC computation logic enable bit 0 (B_0x0): ECC logic is disabled and reset (default after reset), 1 (B_0x1): ECC logic is enabled. |
| TCLR | CLE to RE delay 0 (B_0x0): 1 HCLK cycle (default) 15 (B_0xF): 16 HCLK cycles |
| TAR | ALE to RE delay 0 (B_0x0): 1 HCLK cycle (default) |
| TAR3 | ALE to RE delay 0 (B_0x0): 1 HCLK cycle (default) |
| ECCPS | ECC page size 0 (B_0x0): 256 bytes 1 (B_0x1): 512 bytes 2 (B_0x2): 1024 bytes 3 (B_0x3): 2048 bytes 4 (B_0x4): 4096 bytes 5 (B_0x5): 8192 bytes |