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stm32 /stm32h5 /STM32H523 /FMC /FMC_SDRTR

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Interpret as FMC_SDRTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CRE 0COUNT0 (B_0x0)REIE

REIE=B_0x0, CRE=B_0x0

Description

SDRAM refresh timer register

Fields

CRE

Clear Refresh error flag

0 (B_0x0): no effect

1 (B_0x1): Refresh Error flag is cleared
COUNT

Refresh Timer Count
REIE

RES Interrupt Enable

0 (B_0x0): Interrupt is disabled

1 (B_0x1): An Interrupt is generated if RE = 1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32