PFREQ=B_0x0, SWREQ=B_0x0, DREQ=B_0x0, TRIGM=B_0x0, TRIGPOL=B_0x0, BREQ=B_0x0, TCEM=B_0x0
GPDMA channel 1 transfer register 2
| REQSEL | GPDMA hardware request selection |
| SWREQ | software request 0 (B_0x0): no software request. 1 (B_0x1): software request for a memory-to-memory transfer. |
| DREQ | destination hardware request 0 (B_0x0): selected hardware request driven by a source peripheral (request signal taken into account by the GPDMA transfer scheduler over the source/read port) 1 (B_0x1): selected hardware request driven by a destination peripheral (request signal taken into account by the GPDMA transfer scheduler over the destination/write port) |
| BREQ | Block hardware request 0 (B_0x0): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. 1 (B_0x1): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 16. |
| PFREQ | Hardware request in peripheral flow control mode 0 (B_0x0): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode. 1 (B_0x1): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. |
| TRIGM | trigger mode 0 (B_0x0): at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x (x = 6 to 7), for each block if a 2D/repeated block is configured with GPDMA_CxBR1. 1 (B_0x1): channel x (x = 0 to 5), same as 00; channel x (x = 6 to 7), at 2D/repeated block level. 2 (B_0x2): at link level: a LLI link transfer is conditioned by one hit trigger. 3 (B_0x3): at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. |
| TRIGSEL | trigger event input selection |
| TRIGPOL | trigger event polarity 0 (B_0x0): no trigger (masked trigger event) 1 (B_0x1): trigger on the rising edge 2 (B_0x2): trigger on the falling edge 3 (B_0x3): same as 00 |
| TCEM | transfer complete event mode 0 (B_0x0): at block level (when GPDMA_CxBR1. 1 (B_0x1): channel x (x = 0 to 5), same as 00, channel x (x = 6 to 7), at 2D/repeated block level (when GPDMA_CxBR1. 2 (B_0x2): at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. 3 (B_0x3): at channel level: the complete transfer event is generated at the end of the last LLI transfer. |