stm32 /stm32h5 /STM32H523 /GTZC1_TZSC /GTZC1_TZSC_MPCWM3ACFGR

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Interpret as GTZC1_TZSC_MPCWM3ACFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SREN 0 (B_0x0)SRLOCK 0 (B_0x0)SEC 0 (B_0x0)PRIV

PRIV=B_0x0, SEC=B_0x0, SREN=B_0x0, SRLOCK=B_0x0

Description

GTZC1 TZSC memory 3 subregion A watermark configuration register

Fields

SREN

subregion A enable

0 (B_0x0): subregion A is disabled.

1 (B_0x1): subregion A of region x is enabled.

SRLOCK

subregion A lock

0 (B_0x0): GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR can be written.

1 (B_0x1): Writes to GTZC1_TZSC_MPCWMxCFGR, GTZC1_TZSC_MPCWMxAR and GTZC1_TZSC_MPCWMxBR are ignored.

SEC

Secure subregion A of base region x

0 (B_0x0): Only non-secure data accesses are granted to subregion A of region x.

1 (B_0x1): Only secure data accesses are granted to subregion A of region x.

PRIV

Privileged subregion A of base region x

0 (B_0x0): Privileged and unprivileged accesses are granted in subregion A.

1 (B_0x1): Only privileged accesses are granted in subregion A of region x.

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