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stm32 /stm32h5 /STM32H523 /I2C /I2C_ISR

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Interpret as I2C_ISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXE)TXE 0 (TXIS)TXIS 0 (RXNE)RXNE 0 (ADDR)ADDR 0 (NACKF)NACKF 0 (STOPF)STOPF 0 (TC)TC 0 (TCR)TCR 0 (BERR)BERR 0 (ARLO)ARLO 0 (OVR)OVR 0 (PECERR)PECERR 0 (TIMEOUT)TIMEOUT 0 (ALERT)ALERT 0 (BUSY)BUSY 0 (B_0x0)DIR 0ADDCODE

DIR=B_0x0

Description

I2C interrupt and status register

Fields

TXE

Transmit data register empty (transmitters)
TXIS

Transmit interrupt status (transmitters)
RXNE

Receive data register not empty (receivers)
ADDR

Address matched (slave mode)
NACKF

Not acknowledge received flag
STOPF

Stop detection flag
TC

Transfer complete (master mode)
TCR

Transfer complete reload
BERR

Bus error
ARLO

Arbitration lost
OVR

Overrun/underrun (slave mode)
PECERR

PEC error in reception
TIMEOUT

Timeout or tless thansub>LOWless than/sub> detection flag
ALERT

SMBus alert
BUSY

Bus busy
DIR

Transfer direction (slave mode)

0 (B_0x0): Write transfer, slave enters receiver mode.

1 (B_0x1): Read transfer, slave enters transmitter mode.
ADDCODE

Address match code (slave mode)

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32