stm32 /stm32h5 /STM32H523 /ICACHE /ICACHE_CRR2

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Interpret as ICACHE_CRR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BASEADDR0RSIZE0 (B_0x0)REN 0REMAPADDR0 (B_0x0)MSTSEL 0 (B_0x0)HBURST

REN=B_0x0, MSTSEL=B_0x0, HBURST=B_0x0

Description

ICACHE region 2 configuration register

Fields

BASEADDR

base address for region x

RSIZE

size for region x

1 (B_0x1): 2 Mbytes

2 (B_0x2): 4 Mbytes

3 (B_0x3): 8 Mbytes

4 (B_0x4): 16 Mbytes

5 (B_0x5): 32 Mbytes

6 (B_0x6): 64 Mbytes

7 (B_0x7): 128 Mbytes

REN

enable for region x

0 (B_0x0): disabled

1 (B_0x1): enabled

REMAPADDR

remapped address for region x

MSTSEL

AHB cache master selection for region x

0 (B_0x0): no action (master1 selected by default)

1 (B_0x1): master2 selected

HBURST

output burst type for region x

0 (B_0x0): WRAP

1 (B_0x1): INCR

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