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stm32 /stm32h5 /STM32H523 /PWR /PWR_BDCR

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Interpret as PWR_BDCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BREN 0 (B_0x0)MONEN 0 (B_0x0)VBE 0 (B_0x0)VBRS

MONEN=B_0x0, VBE=B_0x0, BREN=B_0x0, VBRS=B_0x0

Description

PWR Backup domain control register

Fields

BREN

Backup RAM retention in Standby and Vless thansub>BATless than/sub> modes

0 (B_0x0): Backup RAM content lost in Standby and Vless thansub>BATless than/sub> modes.

1 (B_0x1): Backup RAM content preserved in Standby and Vless thansub>BATless than/sub> modes
MONEN

Backup domain voltage and temperature monitoring enable

0 (B_0x0): Backup domain voltage and temperature monitoring disabled

1 (B_0x1): Backup domain voltage and temperature monitoring enabled
VBE

Vless thansub>BATless than/sub> charging enable

0 (B_0x0): Vless thansub>BATless than/sub> battery charging disabled.

1 (B_0x1): Vless thansub>BATless than/sub> battery charging enabled.
VBRS

Vless thansub>BATless than/sub> charging resistor selection

0 (B_0x0): Charge Vless thansub>BATless than/sub> through a 5 kohm resistor.

1 (B_0x1): Charge Vless thansub>BATless than/sub> through a 1.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32