stm32 /stm32h5 /STM32H523 /PWR /PWR_VMCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PWR_VMCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PVDE 0 (B_0x0)PLS0 (B_0x0)AVDEN 0 (B_0x0)ALS

ALS=B_0x0, PVDE=B_0x0, AVDEN=B_0x0, PLS=B_0x0

Description

PWR voltage monitor control register

Fields

PVDE

PVD enable

0 (B_0x0): PVD disabled

1 (B_0x1): PVD enabled

PLS

programmable voltage detector (PVD) level selection

0 (B_0x0): PVD level0 (VPVD0 ~ 1.

1 (B_0x1): PVD level1 (VPVD1 ~ 2.

2 (B_0x2): PVD level2 (VPVD2 ~ 2.

3 (B_0x3): PVD level3 (VPVD3 ~ 2.

4 (B_0x4): PVD level4 (VPVD4 ~ 2.

5 (B_0x5): PVD level5 (VPVD5 ~ 2.

6 (B_0x6): PVD level6 (VPVD6 ~ 2.

7 (B_0x7): PVD_IN pin

AVDEN

peripheral voltage monitor on Vless thansub>DDAless than/sub> enable

0 (B_0x0): peripheral voltage monitor on Vless thansub>DDAless than/sub> disabled

1 (B_0x1): peripheral voltage monitor on Vless thansub>DDAless than/sub> enabled

ALS

analog voltage detector (AVD) level selection

0 (B_0x0): AVD level0 (Vless thansub>AVD0less than/sub> ~ 1.

1 (B_0x1): AVD level1 (Vless thansub>AVD1less than/sub> ~ 2.

2 (B_0x2): AVD level2 (Vless thansub>AVD2less than/sub> ~ 2.

3 (B_0x3): AVD level3 (Vless thansub>AVD3less than/sub> ~ 2.

Links

()