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stm32 /stm32h5 /STM32H523 /RAMCFG /RAMCFG_M5CR

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Interpret as RAMCFG_M5CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ECCE 0 (B_0x0)ALE 0 (B_0x0)SRAMER

SRAMER=B_0x0, ALE=B_0x0, ECCE=B_0x0

Description

RAMCFG memory 5 control register

Fields

ECCE

ECC enable.

0 (B_0x0): ECC disabled

1 (B_0x1): ECC enabled
ALE

Address latch enable

0 (B_0x0): Failing address not stored in the SRAMx ECC single/double error address registers

1 (B_0x1): Failing address stored in the SRAMx ECC single/double error address registers
SRAMER

SRAM erase

0 (B_0x0): No erase operation on going

1 (B_0x1): Erase operation on going

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32