stm32 /stm32h5 /STM32H523 /RCC /RCC_AHB2ENR

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Interpret as RCC_AHB2ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPIOAEN 0 (B_0x0)GPIOBEN 0 (B_0x0)GPIOCEN 0 (B_0x0)GPIODEN 0 (B_0x0)GPIOEEN 0 (B_0x0)GPIOFEN 0 (B_0x0)GPIOGEN 0 (B_0x0)GPIOHEN 0 (B_0x0)GPIOIEN 0 (B_0x0)ADCEN 0 (B_0x0)DAC1EN 0 (B_0x0)DCMI_PSSIEN 0 (B_0x0)AESEN 0 (B_0x0)HASHEN 0 (B_0x0)RNGEN 0 (B_0x0)PKAEN 0 (B_0x0)SAESEN 0 (B_0x0)SRAM2EN 0 (B_0x0)SRAM3EN

DAC1EN=B_0x0, GPIOEEN=B_0x0, GPIOIEN=B_0x0, GPIODEN=B_0x0, GPIOGEN=B_0x0, HASHEN=B_0x0, PKAEN=B_0x0, GPIOAEN=B_0x0, RNGEN=B_0x0, SRAM3EN=B_0x0, DCMI_PSSIEN=B_0x0, AESEN=B_0x0, ADCEN=B_0x0, GPIOHEN=B_0x0, GPIOFEN=B_0x0, SAESEN=B_0x0, GPIOCEN=B_0x0, GPIOBEN=B_0x0, SRAM2EN=B_0x0

Description

RCC AHB2 peripheral clock register

Fields

GPIOAEN

GPIOA clock enable

0 (B_0x0): GPIOA peripheral clock disabled (default after reset)

1 (B_0x1): GPIOA peripheral clock enabled

GPIOBEN

GPIOB clock enable

0 (B_0x0): GPIOB peripheral clock disabled (default after reset)

1 (B_0x1): GPIOB peripheral clock enabled

GPIOCEN

GPIOC clock enable

0 (B_0x0): GPIOC peripheral clock disabled (default after reset)

1 (B_0x1): GPIOC peripheral clock enabled

GPIODEN

GPIOD clock enable

0 (B_0x0): GPIOD peripheral clock disabled (default after reset)

1 (B_0x1): GPIOD peripheral clock enabled

GPIOEEN

GPIOE clock enable

0 (B_0x0): GPIOE peripheral clock disabled (default after reset)

1 (B_0x1): GPIOE peripheral clock enabled

GPIOFEN

GPIOF clock enable

0 (B_0x0): GPIOF peripheral clock disabled (default after reset)

1 (B_0x1): GPIOF peripheral clock enabled

GPIOGEN

GPIOG clock enable

0 (B_0x0): GPIOG peripheral clock disabled (default after reset)

1 (B_0x1): GPIOG peripheral clock enabled

GPIOHEN

GPIOH clock enable

0 (B_0x0): GPIOH peripheral clock disabled (default after reset)

1 (B_0x1): GPIOH peripheral clock enabled

GPIOIEN

GPIOI clock enable

0 (B_0x0): GPIOI peripheral clock disabled (default after reset)

1 (B_0x1): GPIOI peripheral clock enabled

ADCEN

ADC1 and 2 peripherals clock enable

0 (B_0x0): ADC1 and 2 peripherals clock disabled (default after reset)

1 (B_0x1): ADC1 and 2 peripherals clock enabled

DAC1EN

DAC clock enable

0 (B_0x0): DAC peripheral clock disabled (default after reset)

1 (B_0x1): DAC peripheral clock enabled

DCMI_PSSIEN

digital camera interface clock enable (DCMI or PSSI depending which interface is active)

0 (B_0x0): DCMI/PSSI peripheral clock disabled (default after reset)

1 (B_0x1): DCMI/PSSI peripheral clock enabled

AESEN

AES clock enable

0 (B_0x0): AES peripheral clock disabled (default after reset)

1 (B_0x1): AES peripheral clock enabled

HASHEN

HASH clock enable

0 (B_0x0): HASH peripheral clock disabled (default after reset)

1 (B_0x1): HASH peripheral clock enabled

RNGEN

RNG clock enable

0 (B_0x0): RNG peripheral clock disabled (default after reset)

1 (B_0x1): RNG peripheral clock enabled

PKAEN

PKA clock enable

0 (B_0x0): PKA peripheral clock disabled (default after reset)

1 (B_0x1): PKA peripheral clock enabled

SAESEN

SAES clock enable

0 (B_0x0): SAES peripheral clock disabled (default after reset)

1 (B_0x1): SAES peripheral clock enabled

SRAM2EN

SRAM2 clock enable

0 (B_0x0): SRAM2 clock disabled

1 (B_0x1): SRAM2 clock enabled (default after reset)

SRAM3EN

SRAM3 clock enable

0 (B_0x0): SRAM3 clock disabled

1 (B_0x1): SRAM3 clock enabled (default after reset)

Links

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