stm32 /stm32h5 /STM32H523 /RCC /RCC_BDCR

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Interpret as RCC_BDCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LSEON 0 (B_0x0)LSERDY 0 (B_0x0)LSEBYP 0 (B_0x0)LSEDRV 0 (B_0x0)LSECSSON 0 (B_0x0)LSECSSD 0 (B_0x0)LSEEXT 0 (B_0x0)RTCSEL 0 (B_0x0)RTCEN 0 (B_0x0)VSWRST 0 (B_0x0)LSCOEN 0 (B_0x0)LSCOSEL 0 (B_0x0)LSION 0 (B_0x0)LSIRDY

LSIRDY=B_0x0, LSEON=B_0x0, LSCOEN=B_0x0, VSWRST=B_0x0, LSEEXT=B_0x0, LSEDRV=B_0x0, LSEBYP=B_0x0, RTCEN=B_0x0, LSION=B_0x0, LSECSSD=B_0x0, LSECSSON=B_0x0, RTCSEL=B_0x0, LSERDY=B_0x0, LSCOSEL=B_0x0

Description

RCC Backup domain control register

Fields

LSEON

LSE oscillator enabled

0 (B_0x0): LSE oscillator OFF (default after Backup domain reset)

1 (B_0x1): LSE oscillator ON

LSERDY

LSE oscillator ready

0 (B_0x0): LSE oscillator not ready (default after Backup domain reset)

1 (B_0x1): LSE oscillator ready

LSEBYP

LSE oscillator bypass

0 (B_0x0): LSE oscillator not bypassed (default after Backup domain reset)

1 (B_0x1): LSE oscillator bypassed

LSEDRV

LSE oscillator driving capability

0 (B_0x0): lowest drive (default after Backup domain reset)

1 (B_0x1): medium-low drive

2 (B_0x2): medium-high drive

3 (B_0x3): highest drive

LSECSSON

LSE clock security system enable

0 (B_0x0): CSS on 32 kHz oscillator OFF (default after Backup domain reset)

1 (B_0x1): CSS on 32 kHz oscillator ON

LSECSSD

LSE clock security system failure detection

0 (B_0x0): no failure detected on 32 kHz oscillator (default after Backup domain reset)

1 (B_0x1): failure detected on 32 kHz oscillator

LSEEXT

low-speed external clock type in bypass mode

0 (B_0x0): LSE in analog mode (default after Backup domain reset)

1 (B_0x1): LSE in digital mode (do not use if RTC is active).

RTCSEL

RTC clock source selection

0 (B_0x0): no clock (default after Backup domain reset)

1 (B_0x1): LSE selected as RTC clock

2 (B_0x2): LSI selected as RTC clock

3 (B_0x3): HSE divided by RTCPRE value selected as RTC clock

RTCEN

RTC clock enable

0 (B_0x0): rtc_ck disabled (default after Backup domain reset)

1 (B_0x1): rtc_ck enabled

VSWRST

VSwitch domain software reset

0 (B_0x0): reset not activated (default after Backup domain reset)

1 (B_0x1): resets the entire VSW domain

LSCOEN

Low-speed clock output (LSCO) enable

0 (B_0x0): LSCO output disabled

1 (B_0x1): LSCO output enabled

LSCOSEL

Low-speed clock output selection

0 (B_0x0): LSI clock selected

1 (B_0x1): LSE clock selected

LSION

LSI oscillator enable

0 (B_0x0): LSI oscillator off

1 (B_0x1): LSI oscillator on

LSIRDY

LSI oscillator ready

0 (B_0x0): LSI oscillator not ready

1 (B_0x1): LSI oscillator ready

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