APB2DIS=B_0x0, AHB2DIS=B_0x0, APB3DIS=B_0x0, AHB4DIS=B_0x0, APB1DIS=B_0x0, AHB1DIS=B_0x0
RCC CPU domain clock configuration register 2
| HPRE | AHB prescaler 8 (B_0x8): rcc_hclk = sys_ck / 2 9 (B_0x9): rcc_hclk = sys_ck / 4 10 (B_0xA): rcc_hclk = sys_ck / 8 11 (B_0xB): rcc_hclk = sys_ck / 16 12 (B_0xC): rcc_hclk = sys_ck / 64 13 (B_0xD): rcc_hclk = sys_ck / 128 14 (B_0xE): rcc_hclk = sys_ck / 256 15 (B_0xF): rcc_hclk = sys_ck / 512 |
| PPRE1 | APB low-speed prescaler (APB1) 4 (B_0x4): rcc_pclk1 = rcc_hclk1 / 2 5 (B_0x5): rcc_pclk1 = rcc_hclk1 / 4 6 (B_0x6): rcc_pclk1 = rcc_hclk1 / 8 7 (B_0x7): rcc_pclk1 = rcc_hclk1 / 16 |
| PPRE2 | APB high-speed prescaler (APB2) 4 (B_0x4): rcc_pclk2 = rcc_hclk1 / 2 5 (B_0x5): rcc_pclk2 = rcc_hclk1 / 4 6 (B_0x6): rcc_pclk2 = rcc_hclk1 / 8 7 (B_0x7): rcc_pclk2 = rcc_hclk1 / 16 |
| PPRE3 | APB low-speed prescaler (APB3) 4 (B_0x4): rcc_pclk3 = rcc_hclk1 / 2 5 (B_0x5): rcc_pclk3 = rcc_hclk1 / 4 6 (B_0x6): rcc_pclk3 = rcc_hclk1 / 8 7 (B_0x7): rcc_pclk3 = rcc_hclk1 / 16 |
| AHB1DIS | AHB1 clock disable 0 (B_0x0): AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): AHB1 clock disabled |
| AHB2DIS | AHB2 clock disable 0 (B_0x0): AHB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): AHB2 clock disabled |
| AHB4DIS | AHB4 clock disable 0 (B_0x0): AHB4 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): AHB4 clock disabled |
| APB1DIS | APB1 clock disable value 0 (B_0x0): APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): APB1 clock disabled |
| APB2DIS | APB2 clock disable value 0 (B_0x0): APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): APB2 clock disabled |
| APB3DIS | APB3 clock disable value. 0 (B_0x0): APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 1 (B_0x1): APB3 clock disabled |