stm32 /stm32h5 /STM32H523 /RCC /RCC_PLL1DIVR

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Interpret as RCC_PLL1DIVR

PLL1R=B_0x0, PLL1Q=B_0x0, PLL1P=B_0x0

Description

RCC PLL1 dividers register

Fields

PLL1N	Multiplication factor for PLL1VCO 3 (B_0x003): PLL1N = 4 4 (B_0x004): PLL1N = 5 5 (B_0x005): PLL1N = 6 128 (B_0x080): PLL1N = 129 (default after reset) 511 (B_0x1FF): PLL1N = 512
PLL1P	PLL1 DIVP division factor 0 (B_0x0): Not allowed 1 (B_0x1): pll1_p_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): Not allowed 3 (B_0x3): pll1_p_ck = vco1_ck / 4 127 (B_0x7F): pll1_p_ck = vco1_ck / 128
PLL1Q	PLL1 DIVQ division factor 0 (B_0x0): pll1_q_ck = vco1_ck 1 (B_0x1): pll1_q_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_q_ck = vco1_ck / 3 3 (B_0x3): pll1_q_ck = vco1_ck / 4 127 (B_0x7F): pll1_q_ck = vco1_ck / 128
PLL1R	PLL1 DIVR division factor 0 (B_0x0): pll1_r_ck = vco1_ck / 1 1 (B_0x1): pll1_r_ck = vco1_ck / 2 (default after reset) 2 (B_0x2): pll1_r_ck = vco1_ck / 3 3 (B_0x3): pll1_r_ck = vco1_ck / 4 127 (B_0x7F): pll1_r_ck = vco1_ck / 128

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