PLL2PEN=B_0x0, PLL2VCOSEL=B_0x0, PLL2QEN=B_0x0, PLL2RGE=B_0x0, PLL2M=B_0x0, PLL2FRACEN=B_0x0, PLL2REN=B_0x0, PLL2SRC=B_0x0
RCC PLL clock source selection register
| PLL2SRC | PLL2M and PLLs clock source selection 0 (B_0x0): no clock send to PLL2M divider and PLLs (default after reset) 1 (B_0x1): HSI selected as PLL clock (hsi_ck) 2 (B_0x2): CSI selected as PLL clock (csi_ck) 3 (B_0x3): HSE selected as PLL clock (hse_ck) |
| PLL2RGE | PLL2 input frequency range 0 (B_0x0): PLL2 input (ref2_ck) clock range frequency between 1 and 2 MHz (default after reset) 01: PLL2 input (ref2_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz |
| PLL2FRACEN | PLL2 fractional latch enable 0 (B_0x0): pll2_p_ck output disabled (default after reset) 1 (B_0x1): pll2_p_ck output enabled |
| PLL2VCOSEL | PLL2 VCO selection 0 (B_0x0): wide VCO range 192 to 836 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| PLL2M | prescaler for PLL2 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 63 (B_0x3F): division by 63 |
| PLL2PEN | PLL2 DIVP divider output enable 0 (B_0x0): pll2_p_ck output disabled (default after reset) 1 (B_0x1): pll2_p_ck output enabled |
| PLL2QEN | PLL2 DIVQ divider output enable 0 (B_0x0): pll2_q_ck output disabled (default after reset) 1 (B_0x1): pll2_q_ck output enabled |
| PLL2REN | PLL2 DIVR divider output enable 0 (B_0x0): pll2_r_ck output disabled (default after reset) 1 (B_0x1): pll2_r_ck output enabled |