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stm32 /stm32h5 /STM32H523 /RCC /RCC_PLL3DIVR

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Interpret as RCC_PLL3DIVR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL3N0 (B_0x0)PLL3P0 (B_0x0)PLL3Q0 (B_0x0)PLL3R

PLL3Q=B_0x0, PLL3P=B_0x0, PLL3R=B_0x0

Description

RCC PLL3 dividers register

Fields

PLL3N

Multiplication factor for PLL3VCO

3 (B_0x003): PLL3N = 4

4 (B_0x004): PLL3N = 5

5 (B_0x005): PLL3N = 6

128 (B_0x080): PLL3N = 129 (default after reset)

511 (B_0x1FF): PLL3N = 512
PLL3P

PLL3 DIVP division factor

0 (B_0x0): pll3_p_ck = vco3_ck

1 (B_0x1): pll3_p_ck = vco3_ck / 2 (default after reset)

2 (B_0x2): pll3_p_ck = vco3_ck / 3

3 (B_0x3): pll3_p_ck = vco3_ck / 4

127 (B_0x7F): pll3_p_ck = vco3_ck / 128
PLL3Q

PLL3 DIVQ division factor

0 (B_0x0): pll3_q_ck = vco3_ck

1 (B_0x1): pll3_q_ck = vco3_ck / 2 (default after reset)

2 (B_0x2): pll3_q_ck = vco3_ck / 3

3 (B_0x3): pll3_q_ck = vco3_ck / 4

127 (B_0x7F): pll3_q_ck = vco3_ck / 128
PLL3R

PLL3 DIVR division factor

0 (B_0x0): pll3_r_ck = vco3_ck

1 (B_0x1): pll3_r_ck = vco3_ck / 2 (default after reset)

2 (B_0x2): pll3_r_ck = vco3_ck / 3

3 (B_0x3): pll3_r_ck = vco3_ck / 4

127 (B_0x7F): pll3_r_ck = vco3_ck / 128

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32