stm32 /stm32h5 /STM32H523 /SBS /SBS_CFGR2

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Interpret as SBS_CFGR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CLL 0 (B_0x0)SEL 0 (B_0x0)PVDL 0 (B_0x0)ECCL

CLL=B_0x0, PVDL=B_0x0, SEL=B_0x0, ECCL=B_0x0

Description

SBS Class B register

Fields

CLL

core lockup lock

0 (B_0x0): lockup output disconnected from timer break inputs

1 (B_0x1): lockup output connected to timer break inputs

SEL

SRAM ECC error lock

0 (B_0x0): SRAM double ECC error flag disconnected from timer break inputs

1 (B_0x1): SRAM double ECC error flag connected to timer break inputs

PVDL

PVD lock

0 (B_0x0): PVD interrupt disconnected from timer break inputs.

1 (B_0x1): PVD interrupt is connected to timer break inputs.

ECCL

ECC lock

0 (B_0x0): double ECC error flag disconnected to timer break inputs

1 (B_0x1): double ECC error flag connected to timer break inputs

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