stm32 /stm32h5 /STM32H523 /SBS /SBS_SECCFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SBS_SECCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SBSSEC 0 (B_0x0)CLASSBSEC 0 (B_0x0)FPUSEC

CLASSBSEC=B_0x0, FPUSEC=B_0x0, SBSSEC=B_0x0

Description

SBS security mode configuration control register

Fields

SBSSEC

SBS clock control, memory-erase status register and compensation cell register security enable

0 (B_0x0): SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible through secure or non-secure transaction

1 (B_0x1): SBS_MESR, SBS_CCCSR, SBS_CCVALR, SBS_CCSWCR registers accessible only through secure transaction

CLASSBSEC

ClassB security enable

0 (B_0x0): SBS_CFGR2 register accessible through secure or non-secure transaction

1 (B_0x1): SBS_CFGR2 register accessible only through secure transaction

FPUSEC

FPU security enable

0 (B_0x0): SBS_FPUIMP register accessible through secure or non-secure transaction

1 (B_0x1): SBS_FPUIMP register accessible only through secure transaction

Links

()