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stm32 /stm32h5 /STM32H523 /SDMMC /SDMMC_IDMALAR

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Interpret as SDMMC_IDMALAR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IDMALA0 (B_0x0)ABR 0 (B_0x0)ULS 0 (B_0x0)ULA

ULA=B_0x0, ULS=B_0x0, ABR=B_0x0

Description

SDMMC IDMA linked list address register

Fields

IDMALA

Word aligned linked list item address offset
ABR

Acknowledge linked list buffer ready

0 (B_0x0): Loaded linked list buffer is not ready (this causes a linked list IDMA transfer error to be generated).

1 (B_0x1): Loaded linked list buffer ready acknowledge.
ULS

Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.

0 (B_0x0): SDMMC_IDMABSIZER is not to be updated from next linked list table.

1 (B_0x1): SDMMC_IDMABSIZER is to be updated from next linked list table.
ULA

Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.

0 (B_0x0): SDMMC_IDMALAR is not to be updated, last linked list item.

1 (B_0x1): SDMMC_IDMALAR is to be updated from linked list table.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32