CRC33_17=B_0x0, RCRCINI=B_0x0, HDDIR=B_0x0, CSTART=B_0x0, MASRX=B_0x0, SPE=B_0x0, IOLOCK=B_0x0, TCRCINI=B_0x0
SPI/I2S control register 1
| SPE | serial peripheral enable 0 (B_0x0): Serial peripheral disabled. 1 (B_0x1): Serial peripheral enabled |
| MASRX | master automatic suspension in Receive mode 0 (B_0x0): SPI flow/clock generation is continuous, regardless of overrun condition. 1 (B_0x1): SPI flow is suspended temporary on RxFIFO full condition, before reaching overrun condition. |
| CSTART | master transfer start 0 (B_0x0): master transfer is at idle 1 (B_0x1): master transfer is ongoing or temporary suspended by automatic suspend |
| CSUSP | master suspend request |
| HDDIR | Rx/Tx direction at half-duplex mode 0 (B_0x0): SPI is receiver 1 (B_0x1): SPI is transmitter |
| SSI | internal SS signal input level |
| CRC33_17 | 32-bit CRC polynomial configuration 0 (B_0x0): Full size (33-bit or 17-bit) CRC polynomial is not used 1 (B_0x1): Full size (33-bit or 17-bit) CRC polynomial is used |
| RCRCINI | CRC calculation initialization pattern control for receiver 0 (B_0x0): All zero pattern is applied 1 (B_0x1): All ones pattern is applied |
| TCRCINI | CRC calculation initialization pattern control for transmitter 0 (B_0x0): all zero pattern is applied 1 (B_0x1): all ones pattern is applied |
| IOLOCK | locking the AF configuration of associated I/Os 0 (B_0x0): AF configuration is not locked 1 (B_0x1): AF configuration is locked |