CEN=B_0x0, DITHEN=B_0x0, CKD=B_0x0, UDIS=B_0x0, UIFREMAP=B_0x0, OPM=B_0x0, ARPE=B_0x0, URS=B_0x0
TIM15 control register 1
| CEN | Counter enable 0 (B_0x0): Counter disabled 1 (B_0x1): Counter enabled |
| UDIS | Update disable 0 (B_0x0): UEV enabled. 1 (B_0x1): UEV disabled. |
| URS | Update request source 0 (B_0x0): Any of the following events generate an update interrupt if enabled. 1 (B_0x1): Only counter overflow/underflow generates an update interrupt if enabled |
| OPM | One-pulse mode 0 (B_0x0): Counter is not stopped at update event 1 (B_0x1): Counter stops counting at the next update event (clearing the bit CEN) |
| ARPE | Auto-reload preload enable 0 (B_0x0): TIM15_ARR register is not buffered 1 (B_0x1): TIM15_ARR register is buffered |
| CKD | Clock division 0 (B_0x0): tless thansub>DTS less than/sub>= tless thansub>tim_ker_ckless than/sub> 1 (B_0x1): tless thansub>DTSless than/sub> = 2*tless thansub>tim_ker_ckless than/sub> 2 (B_0x2): tless thansub>DTSless than/sub> = 4*tless thansub>tim_ker_ckless than/sub> |
| UIFREMAP | UIF status bit remapping 0 (B_0x0): No remapping. 1 (B_0x1): Remapping enabled. |
| DITHEN | Dithering enable 0 (B_0x0): Dithering disabled 1 (B_0x1): Dithering enabled |