RXDMAEN=B_0x0, TRANSWIN=B_0x00, IFRGAP=B_0x00, PSC_USBPDCLK=B_0x0, UCPDEN=B_0x0, HBITCLKDIV=B_0x00, TXDMAEN=B_0x0
UCPD configuration register 1
| HBITCLKDIV | Division ratio for producing half-bit clock 0 (B_0x00): 1 (bypass) 26 (B_0x1A): 27 63 (B_0x3F): 64 |
| IFRGAP | Division ratio for producing inter-frame gap timer clock 0 (B_0x00): Not supported 1 (B_0x01): 2 13 (B_0x0D): 14 14 (B_0x0E): 15 15 (B_0x0F): 16 31 (B_0x1F): 32 |
| TRANSWIN | Transition window duration 0 (B_0x00): Not supported 1 (B_0x01): 2 9 (B_0x09): 10 (recommended) 31 (B_0x1F): 32 |
| PSC_USBPDCLK | Pre-scaler division ratio for generating ucpd_clk 0 (B_0x0): 1 (bypass) 1 (B_0x1): 2 2 (B_0x2): 4 3 (B_0x3): 8 4 (B_0x4): 16 |
| RXORDSETEN | Receiver ordered set enable |
| TXDMAEN | Transmission DMA mode enable 0 (B_0x0): Disable 1 (B_0x1): Enable |
| RXDMAEN | Reception DMA mode enable 0 (B_0x0): Disable 1 (B_0x1): Enable |
| UCPDEN | UCPD peripheral enable 0 (B_0x0): Disable 1 (B_0x1): Enable |