stm32 /stm32h5 /STM32H533 /ADCC /ADC_HWCFGR0

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Interpret as ADC_HWCFGR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADCNUM0MULPIPE0 (B_0x0)OPBITS0 (B_0x0)IDLEVALUE

OPBITS=B_0x0, IDLEVALUE=B_0x0

Description

ADC hardware configuration register

Fields

ADCNUM

Number of ADCs implemented

1 (B_0x1): One ADC instance implemented

2 (B_0x2): Two ADC instances implemented

3 (B_0x3): Three ADCs instances implemented

MULPIPE

Number of pipeline stages

1 (B_0x1): One-stage pipeline

OPBITS

Number of option bits

0 (B_0x0): No option register implemented

1 (B_0x1): 1 option bit implemented in the ADC option register (ADC_OR) at address offset 0xC8

IDLEVALUE

Idle value for non-selected channels

0 (B_0x0): Dummy channel selection is 0x13

1 (B_0x1): Dummy channel selection is 0x1F

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