stm32 /stm32h5 /STM32H533 /AES /AES_CR

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Interpret as AES_CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EN 0 (B_0x0)DATATYPE 0 (B_0x0)MODE 0 (B_0x0)CHMOD 0 (B_0x0)DMAINEN 0 (B_0x0)DMAOUTEN 0 (B_0x0)GCMPH 0 (CHMOD_1)CHMOD_1 0 (B_0x0)KEYSIZE 0 (B_0x0)NPBLB0 (B_0x0)KMOD 0 (IPRST)IPRST

DMAINEN=B_0x0, DATATYPE=B_0x0, EN=B_0x0, GCMPH=B_0x0, NPBLB=B_0x0, CHMOD=B_0x0, KEYSIZE=B_0x0, MODE=B_0x0, DMAOUTEN=B_0x0, KMOD=B_0x0

Description

AES control register

Fields

EN

Enable

0 (B_0x0): Disable

1 (B_0x1): Enable

DATATYPE

Data type

0 (B_0x0): No swapping (32-bit data).

1 (B_0x1): Half-word swapping (16-bit data)

2 (B_0x2): Byte swapping (8-bit data)

3 (B_0x3): Bit-level swapping

MODE

Operating mode

0 (B_0x0): Encryption

1 (B_0x1): Key derivation (or key preparation), for ECB/CBC decryption only

2 (B_0x2): Decryption

CHMOD

CHMOD[1:0]: Chaining mode

0 (B_0x0): Electronic codebook (ECB)

1 (B_0x1): Cipher-block chaining (CBC)

2 (B_0x2): Counter mode (CTR)

3 (B_0x3): Galois counter mode (GCM) and Galois message authentication code (GMAC)

DMAINEN

DMA input enable

0 (B_0x0): Disable

1 (B_0x1): Enable

DMAOUTEN

DMA output enable

0 (B_0x0): Disable

1 (B_0x1): Enable

GCMPH

GCM or CCM phase selection

0 (B_0x0): Initialization phase

1 (B_0x1): Header phase

2 (B_0x2): Payload phase

3 (B_0x3): Final phase

CHMOD_1

CHMOD[2]

KEYSIZE

Key size selection

0 (B_0x0): 128-bit

1 (B_0x1): 256-bit

NPBLB

Number of padding bytes in last block

0 (B_0x0): All bytes are valid (no padding)

1 (B_0x1): Padding for the last LSB byte

15 (B_0xF): Padding for the 15 LSB bytes of last block.

KMOD

Key mode selection

0 (B_0x0): Normal key mode.

2 (B_0x2): Shared key mode.

IPRST

AES peripheral software reset

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