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stm32 /stm32h5 /STM32H533 /DBGMCU /DBGMCU_AHB1FZR

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Interpret as DBGMCU_AHB1FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_GPDMA1_0_STOP 0 (B_0x0)DBG_GPDMA1_1_STOP 0 (B_0x0)DBG_GPDMA1_2_STOP 0 (B_0x0)DBG_GPDMA1_3_STOP 0 (B_0x0)DBG_GPDMA1_4_STOP 0 (B_0x0)DBG_GPDMA1_5_STOP 0 (B_0x0)DBG_GPDMA1_6_STOP 0 (B_0x0)DBG_GPDMA1_7_STOP 0 (B_0x0)DBG_GPDMA2_0_STOP 0 (B_0x0)DBG_GPDMA2_1_STOP 0 (B_0x0)DBG_GPDMA2_2_STOP 0 (B_0x0)DBG_GPDMA2_3_STOP 0 (B_0x0)DBG_GPDMA2_4_STOP 0 (B_0x0)DBG_GPDMA2_5_STOP 0 (B_0x0)DBG_GPDMA2_6_STOP 0 (B_0x0)DBG_GPDMA2_7_STOP

DBG_GPDMA1_1_STOP=B_0x0, DBG_GPDMA1_6_STOP=B_0x0, DBG_GPDMA2_2_STOP=B_0x0, DBG_GPDMA2_7_STOP=B_0x0, DBG_GPDMA2_4_STOP=B_0x0, DBG_GPDMA1_4_STOP=B_0x0, DBG_GPDMA1_5_STOP=B_0x0, DBG_GPDMA1_0_STOP=B_0x0, DBG_GPDMA2_6_STOP=B_0x0, DBG_GPDMA2_3_STOP=B_0x0, DBG_GPDMA1_2_STOP=B_0x0, DBG_GPDMA2_0_STOP=B_0x0, DBG_GPDMA2_1_STOP=B_0x0, DBG_GPDMA1_7_STOP=B_0x0, DBG_GPDMA1_3_STOP=B_0x0, DBG_GPDMA2_5_STOP=B_0x0

Description

DBGMCU AHB1 peripheral freeze register

Fields

DBG_GPDMA1_0_STOP

GPDMA1 channel 0 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_1_STOP

GPDMA1 channel 1 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_2_STOP

GPDMA1 channel 2 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_3_STOP

GPDMA1 channel 3 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_4_STOP

GPDMA1 channel 4 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_5_STOP

GPDMA1 channel 5 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_6_STOP

GPDMA1 channel 6 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA1_7_STOP

GPDMA1 channel 7 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_0_STOP

GPDMA2 channel 0 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_1_STOP

GPDMA2 channel 1 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_2_STOP

GPDMA2 channel 2 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_3_STOP

GPDMA2 channel 3 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_4_STOP

GPDMA2 channel 4 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_5_STOP

GPDMA2 channel 5 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_6_STOP

GPDMA2 channel 6 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.
DBG_GPDMA2_7_STOP

GPDMA2 channel 7 stop in debug

0 (B_0x0): normal operation.

1 (B_0x1): stop in debug.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32