MSM=B_0x0, SMS=B_0x0, TS_2=B_0x0, TS=B_0x0, SMS_2=B_0x0
TIM12 slave mode control register
| SMS | Slave mode selection 0 (B_0x0): Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. 1 (B_0x1): Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. 2 (B_0x2): Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level. 3 (B_0x3): Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input. 4 (B_0x4): Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers. 5 (B_0x5): Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 6 (B_0x6): Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset). Only the start of the counter is controlled. 7 (B_0x7): External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter. |
| TS | Trigger selection (see bits 21:20 for TS[4:3]) 0 (B_0x0): Internal trigger 0 (tim_itr0) 1 (B_0x1): Internal trigger 1 (tim_itr1) 2 (B_0x2): Internal trigger 2 (tim_itr2) 3 (B_0x3): Internal trigger 3 (tim_itr3) 4 (B_0x4): tim_ti1 edge detector (tim_ti1f_ed) 5 (B_0x5): Filtered timer input 1 (tim_ti1fp1) 6 (B_0x6): Filtered timer input 2 (tim_ti2fp2) 7 (B_0x7): External trigger input (tim_etrf) |
| MSM | Master/Slave mode 0 (B_0x0): No action 1 (B_0x1): The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo). It is useful if we want to synchronize several timers on a single external event. |
| SMS_2 | Slave mode selection 0 (B_0x0): Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock. 1 (B_0x1): Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level. |
| TS_2 | Trigger selection (see bits 21:20 for TS[4:3]) 0 (B_0x0): Internal trigger 0 (tim_itr0) 1 (B_0x1): Internal trigger 1 (tim_itr1) 2 (B_0x2): Internal trigger 2 (tim_itr2) 3 (B_0x3): Internal trigger 3 (tim_itr3) |