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stm32 /stm32h5 /STM32H533 /TIM12 /TIM12_SR

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Interpret as TIM12_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)UIF 0 (B_0x0)CC1IF 0 (CC2IF)CC2IF 0 (B_0x0)TIF 0 (B_0x0)CC1OF 0 (CC2OF)CC2OF

TIF=B_0x0, UIF=B_0x0, CC1OF=B_0x0, CC1IF=B_0x0

Description

TIM12 status register

Fields

UIF

Update interrupt flag

0 (B_0x0): No update occurred

1 (B_0x1): Update interrupt pending. This bit is set by hardware when the registers are updated:
CC1IF

Capture/compare 1 interrupt flag

0 (B_0x0): No compare match / No input capture occurred

1 (B_0x1): A compare match or an input capture occurred
CC2IF

Capture/Compare 2 interrupt flag
TIF

Trigger interrupt flag

0 (B_0x0): No trigger event occurred.

1 (B_0x1): Trigger interrupt pending.
CC1OF

Capture/Compare 1 overcapture flag

0 (B_0x0): No overcapture has been detected.

1 (B_0x1): The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
CC2OF

Capture/compare 2 overcapture flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32