RWMOD=B_0x0, DBLOCKSIZE=B_0x0, BOOTACKEN=B_0x0, RWSTOP=B_0x0, DTDIR=B_0x0, FIFORST=B_0x0, DTMODE=B_0x0, DTEN=B_0x0
SDMMC data control register
| DTEN | Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. 0 (B_0x0): Do not start data transfer without CPSM data transfer command. 1 (B_0x1): Start data transfer without CPSM data transfer command. |
| DTDIR | Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 (B_0x0): From host to card. 1 (B_0x1): From card to host. |
| DTMODE | Data transfer mode selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 (B_0x0): Block data transfer ending on block count. 1 (B_0x1): SDIO multibyte data transfer. 2 (B_0x2): e MMC Stream data transfer. (WIDBUS must select 1-bit wide bus mode) 3 (B_0x3): Block data transfer ending with STOP_TRANSMISSION command (not to be used with DTEN initiated data transfers). |
| DBLOCKSIZE | Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (None of the remaining data are transfered.) When DDR = 1, DBLOCKSIZE = 0000 must not be used. (No data are transfered) 0 (B_0x0): Block length = 20 = 1 byte 1 (B_0x1): Block length = 21 = 2 bytes 2 (B_0x2): Block length = 22 = 4 bytes 3 (B_0x3): Block length = 23 = 8 bytes 4 (B_0x4): Block length = 24 = 16 bytes 5 (B_0x5): Block length = 25 = 32 bytes 6 (B_0x6): Block length = 26 = 64 bytes 7 (B_0x7): Block length = 27 = 128 bytes 8 (B_0x8): Block length = 28 = 256 bytes 9 (B_0x9): Block length = 29 = 512 bytes 10 (B_0xA): Block length = 210 = 1024 bytes 11 (B_0xB): Block length = 211 = 2048 bytes 12 (B_0xC): Block length = 212 = 4096 bytes 13 (B_0xD): Block length = 213 = 8192 bytes 14 (B_0xE): Block length = 214 = 16384 bytes |
| RWSTART | Read Wait start If this bit is set, Read Wait operation starts. |
| RWSTOP | Read Wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the R_W state to the Wait_R or Idle state. 0 (B_0x0): No Read Wait stop. 1 (B_0x1): Enable for Read Wait stop when DPSM is in the R_W state. |
| RWMOD | Read Wait mode This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 (B_0x0): Read Wait control using SDMMC_D2 1 (B_0x1): Read Wait control stopping SDMMC_CK |
| SDIOEN | SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation. |
| BOOTACKEN | Enable the reception of the boot acknowledgment This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 (B_0x0): Boot acknowledgment disabled, not expected to be received 1 (B_0x1): Boot acknowledgment enabled, expected to be received |
| FIFORST | FIFO reset, flushes any remaining data This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit only takes effect when a transfer error or transfer hold occurs. 0 (B_0x0): FIFO not affected. 1 (B_0x1): Flush any remaining data and reset the FIFO pointers. This bit is automatically cleared to 0 by hardware when DPSM gets inactive (DPSMACT = 0). |