stm32 /stm32h5 /STM32H563 /FMC /FMC_BCR2

Memory bank enable bit Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.

0 (B_0x0): Corresponding memory bank is disabled.

1 (B_0x1): Corresponding memory bank is enabled.

Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:

0 (B_0x0): Address/data non multiplexed

1 (B_0x1): Address/data multiplexed on databus (default after reset)

Memory type Defines the type of external memory attached to the corresponding memory bank.

0 (B_0x0): SRAM/FRAM (default after reset for Bank 2…4)

1 (B_0x1): PSRAM (CRAM) / FRAM

2 (B_0x2): NOR Flash/OneNAND Flash (default after reset for Bank 1)

Memory data bus width Defines the external memory device width, valid for all type of memories.

0 (B_0x0): 8 bits

1 (B_0x1): 16 bits (default after reset)

Flash access enable Enables NOR Flash memory access operations.

0 (B_0x0): Corresponding NOR Flash memory access is disabled.

1 (B_0x1): Corresponding NOR Flash memory access is enabled (default after reset).

Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode.

0 (B_0x0): Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.

1 (B_0x1): Burst mode enable. Read accesses are performed in Synchronous mode.

Wait signal polarity bit Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous mode.

0 (B_0x0): NWAIT active low (default after reset)

1 (B_0x1): NWAIT active high

Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in Synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:

0 (B_0x0): NWAIT signal is active one data cycle before wait state (default after reset).

1 (B_0x1): NWAIT signal is active during wait state (not used for PSRAM).

Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC.

0 (B_0x0): Write operations are disabled in the bank by the FMC, an AHB error is reported.

1 (B_0x1): Write operations are enabled for the bank by the FMC (default after reset).

Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in Synchronous mode.

0 (B_0x0): NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period).

1 (B_0x1): NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset).

Extended mode enable This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows: Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01) Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

0 (B_0x0): values inside FMC_BWTR register are not taken into account (default after reset)

1 (B_0x1): values inside FMC_BWTR register are taken into account

Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.

0 (B_0x0): NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset).

1 (B_0x1): NWAIT signal is taken in to account when running an asynchronous protocol.

CRAM page size These are used for CellularRAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Others: reserved

0 (B_0x0): No burst split when crossing page boundary (default after reset)

1 (B_0x1): 128 bytes

2 (B_0x2): 256 bytes

3 (B_0x3): 512 bytes

4 (B_0x4): 1024 bytes

Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

0 (B_0x0): Write operations are always performed in Asynchronous mode.

1 (B_0x1): Write operations are performed in Synchronous mode.

Continuous clock enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2…4 registers is don’t care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the FMC_CLK continuous clock. Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care. Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2…4 and FMC_BWTR2…4 registers for other banks has no effect.)

0 (B_0x0): The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset).

1 (B_0x1): The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set.

Write FIFO disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2…4 registers is don’t care. It is only enabled through the FMC_BCR1 register.

0 (B_0x0): Write FIFO enabled (Default after reset)

1 (B_0x1): Write FIFO disabled

Byte lane (NBL) setup These bits configure the NBL setup timing from NBLx low to chip select NEx low.

0 (B_0x0): NBL setup time is 0 AHB clock cycle

1 (B_0x1): NBL setup time is 1 AHB clock cycle

2 (B_0x2): NBL setup time is 2 AHB clock cycles

3 (B_0x3): NBL setup time is 3 AHB clock cycles

FMC controller enable This bit enables or disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2…4 registers is don’t care. It is only enabled through the FMC_BCR1 register.

0 (B_0x0): Disable the FMC controller

1 (B_0x1): Enable the FMC controller