stm32 /stm32h5 /STM32H563 /FMC /FMC_BTR1

Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 21 to Figure 33), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM: … For each access mode address setup phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is don’t care. Note: In Muxed mode or mode D, the minimum value for ADDSET is 1. Note: In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

0 (B_0x0): ADDSET phase duration = 0 HCLK clock cycle

15 (B_0xF): ADDSET phase duration = 15 HCLK clock cycles (default value after reset)

Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 21 to Figure 33), used in mode D or multiplexed accesses: … For each access mode address-hold phase duration, refer to the respective figure (Figure 21 to Figure 33). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

1 (B_0x1): ADDHLD phase duration =1 HCLK clock cycle

2 (B_0x2): ADDHLD phase duration = 2 HCLK clock cycle

15 (B_0xF): ADDHLD phase duration = 15 HCLK clock cycles (default value after reset)

Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous accesses: For each memory type and access mode data-phase duration, refer to the respective figure (Figure 21 to Figure 33). Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care.

1 (B_0x1): DATAST phase duration = 1 HCLK clock cycles

2 (B_0x2): DATAST phase duration = 2 HCLK clock cycles

255 (B_0xFF): DATAST phase duration = 255 HCLK clock cycles (default value after reset)

Bus turnaround phase duration These bits are written by software to add a delay at the end of current read or write transaction to next transaction on the same bank. This delay allows to match the minimum time between consecutive transactions (tsub EHEL/sub from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tsub EHQZ/sub , chip enable high to output Hi-Z). This delay is recommended for mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to minimum value. (BUSTURN + 1)HCLK period greater than or equal max(tsub EHEL/sub min, tsub EHQZ/sub max) For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read) to match the tPC memory timing. The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period greater than or equal tsub PC/sub min …

0 (B_0x0): BUSTURN phase duration = 1 HCLK clock cycle added

15 (B_0xF): BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset)

Clock divide ratio (for FMC_CLK signal) Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Note: Refer to Section 5.6.5: Synchronous transactions for FMC_CLK divider ratio formula)

0 (B_0x0): FMC_CLK period= 1x HCLK period

1 (B_0x1): FMC_CLK period = 2 HCLK periods

2 (B_0x2): FMC_CLK period = 3 HCLK periods

15 (B_0xF): FMC_CLK period = 16 HCLK periods (default value after reset)

(see note below bit descriptions): Data latency for synchronous memory For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data: This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods. For asynchronous access, this value is don’t care.

0 (B_0x0): Data latency of 2 CLK clock cycles for first burst access

15 (B_0xF): Data latency of 17 CLK clock cycles for first burst access (default value after reset)

Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

0 (B_0x0): Access mode A

1 (B_0x1): Access mode B

2 (B_0x2): Access mode C

3 (B_0x3): Access mode D

Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: For read accesses For write accesses

0 (B_0x0): DATAHLD phase duration = 1 HCLK clock cycle (default)

1 (B_0x1): DATAHLD phase duration = 2 HCLK clock cycle

2 (B_0x2): DATAHLD phase duration = 3 HCLK clock cycle

3 (B_0x3): DATAHLD phase duration = 4 HCLK clock cycle