ADDSET=B_0x0, BUSTURN=B_0x0, DATAHLD=B_0x0, ACCMOD=B_0x0
SRAM/NOR-Flash write timing registers 1
| ADDSET | Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: … Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1. 0 (B_0x0): ADDSET phase duration = 0 HCLK clock cycle 15 (B_0xF): ADDSET phase duration = 15 HCLK clock cycles (default value after reset) |
| ADDHLD | Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: … Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. 1 (B_0x1): ADDHLD phase duration = 1 HCLK clock cycle 2 (B_0x2): ADDHLD phase duration = 2 HCLK clock cycle 15 (B_0xF): ADDHLD phase duration = 15 HCLK clock cycles (default value after reset) |
| DATAST | Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: … 1 (B_0x1): DATAST phase duration = 1 HCLK clock cycles 2 (B_0x2): DATAST phase duration = 2 HCLK clock cycles 255 (B_0xFF): DATAST phase duration = 255 HCLK clock cycles (default value after reset) |
| BUSTURN | Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tsub PC/sub (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period greater than or equal tPC min … 0 (B_0x0): BUSTURN phase duration = 1 HCLK clock cycle added 15 (B_0xF): BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset) |
| ACCMOD | Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 0 (B_0x0): Access mode A 1 (B_0x1): Access mode B 2 (B_0x2): Access mode C 3 (B_0x3): Access mode D |
| DATAHLD | Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses: 0 (B_0x0): DATAHLD phase duration = 1 HCLK clock cycle (default) 1 (B_0x1): DATAHLD phase duration = 2 HCLK clock cycle 2 (B_0x2): DATAHLD phase duration = 3 HCLK clock cycle 3 (B_0x3): DATAHLD phase duration = 4 HCLK clock cycle |