TRP=B_0x0, TRCD=B_0x0, TMRD=B_0x0, TWR=B_0x0, TXSR=B_0x0, TRAS=B_0x0, TRC=B_0x0
SDRAM timing registers 1
| TMRD | Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. … 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TXSR | Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. … Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device. 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRAS | Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. … 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRC | Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. … Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are don’t care. 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TWR | Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. … Note: TWR must be programmed to match the write recovery time (tsub WR/sub ) defined in the SDRAM datasheet, and to guarantee that: Note: TWR greater than or equal TRASTRCD and TWR greater than or equalTRCTRCDTRP Note: Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR = 2 cycles. TWR must be programmed to 0x1. Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device. Note: If only one SDRAM device is used, the TWR timing must be kept at reset value (0xF) for the not used bank. 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRP | Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. … Note: The corresponding bits in the FMC_SDTR2 register are don’t care. 0 (B_0x0): 1 cycle 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |
| TRCD | Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. … 0 (B_0x0): 1 cycle. 1 (B_0x1): 2 cycles 15 (B_0xF): 16 cycles |