IC1F=B_0x0, CC2P=B_0x0_CC2_AS_OUTPUT, CC2E=B_0x0_CC2_AS_OUTPUT, CC1E=B_0x0_CC1_AS_OUTPUT, CC1SEL=B_0x0, CC2SEL=B_0x0, IC2PSC=B_0x0, IC1PSC=B_0x0, CC1P=B_0x0_CC1_AS_OUTPUT, IC2F=B_0x0
LPTIM capture/compare mode register 1
| CC1SEL | Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. 0 (B_0x0): CC1 channel is configured in output PWM mode 1 (B_0x1): CC1 channel is configured in input capture mode |
| CC1E | Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. 0 (B_0x0_CC1_AS_OUTPUT): OffOC1 is not active. Writing ‘0’ to the CC1E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled. 1 (B_0x1_CC1_AS_OUTPUT): OnOC1 signal is output on the corresponding output pin |
| CC1P | Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don’t care. This field is used to select the IC1 polarity for capture operations. 0 (B_0x0_CC1_AS_OUTPUT): OC1 active high, the LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CCRx registers 1 (B_0x1_CC1_AS_OUTPUT): OC1 active low, the LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CCRx registers 2 (B_0x2_CC1_AS_INPUT): reserved, do not use this configuration. 3 (B_0x3_CC1_AS_INPUT): both edges, circuit is sensitive to both IC1 rising and falling edges. |
| IC1PSC | Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). 0 (B_0x0): no prescaler, capture is done each time an edge is detected on the capture input 1 (B_0x1): capture is done once every 2 events 2 (B_0x2): capture is done once every 4 events 3 (B_0x3): capture is done once every 8 events |
| IC1F | Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. 0 (B_0x0): any external input capture signal level change is considered as a valid transition 1 (B_0x1): external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 2 (B_0x2): external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 3 (B_0x3): external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. |
| CC2SEL | Capture/compare 2 selection This bitfield defines the direction of the channel, input (capture) or output mode. 0 (B_0x0): CC2 channel is configured in output PWM mode 1 (B_0x1): CC2 channel is configured in input capture mode |
| CC2E | Capture/compare 2 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 2 (LPTIM_CCR2) or not. 0 (B_0x0_CC2_AS_OUTPUT): OffOC2 is not active. Writing ‘0’ to the CC2E bit resets the ue_dma_req signal only if all the other LPTIM channels are disabled. 1 (B_0x1_CC2_AS_OUTPUT): OnOC2 signal is output on the corresponding output pin |
| CC2P | Capture/compare 2 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don’t care. This field is used to select the IC2 polarity for capture operations. 0 (B_0x0_CC2_AS_OUTPUT): OC2 active high 1 (B_0x1_CC2_AS_OUTPUT): OC2 active low 2 (B_0x2_CC2_AS_INPUT): reserved, do not use this configuration. 3 (B_0x3_CC2_AS_INPUT): both edges, circuit is sensitive to both IC2 rising and falling edges. |
| IC2PSC | Input capture 2 prescaler This bitfield defines the ratio of the prescaler acting on the CC2 input (IC2). 0 (B_0x0): no prescaler, capture is done each time an edge is detected on the capture input 1 (B_0x1): capture is done once every 2 events 2 (B_0x2): capture is done once every 4 events 3 (B_0x3): capture is done once every 8 events |
| IC2F | Input capture 2 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. 0 (B_0x0): any external input capture signal level change is considered as a valid transition 1 (B_0x1): external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 2 (B_0x2): external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 3 (B_0x3): external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition. |